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Course Intro
NPTEL - VLSI Design Flow: RTL to GDS, IIIT Delhi - Prof. Sneh Saurabh
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NPTEL-NOC IITM
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Prof. Sneh Saurabh ECE, IIIT Delhi. VLSI Design Flow: RTL to GDS - Course Intro
Course content
0 of 56 completed
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39h 17m left
Course Intro
10:01
2
Basic Concepts of Integrated Circuit - I
48:58
3
Basic Concepts of Integrated Circuit - II
37:48
4
Overview of VLSI Design Flow - I
47:16
5
Overview of VLSI Design Flow - II
46:04
6
Tutorial 1
10:46
7
Overview of VLSI Design Flow - III
43:02
8
Overview of VLSI Design Flow - IV
54:43
9
Overview of VLSI Design Flow - V
59:17
10
Overview of VLSI Design Flow - VI
28:43
11
Introduction to TCL
10:38
12
Hardware Modeling: Introduction to Verilog-I
46:12
13
Hardware Modeling: Introduction to Verilog-II
48:27
14
Functional Verification using Simulation
1:04:57
15
High-level synthesis using Bambu - Tutorial 3
7:14
16
RTL Synthesis- Part I
55:10
17
RTL Synthesis- Part II
35:03
18
Logic Optimization: Part I
1:10:52
19
Simulation-based Verification using Icarus
15:40
20
Logic Optimization: Part II
1:09:46
21
Logic Optimization: Part III
33:48
22
Formal Verification-I
1:07:14
23
Logic Synthesis using Yosys
7:34
24
Formal Verification-II
34:22
25
Formal Verification-III
1:04:02
26
Formal Verification-IV
39:55
27
Technology Library
1:02:32
28
Logic Optimization using Yosys
14:47
29
Static Timing Analysis- I
52:40
30
Static Timing Analysis- II
1:14:16
31
Static Timing Analysis- III
1:00:39
32
Static Timing Analysis using OpenSTA
14:08
33
Constraints I
54:44
34
Constraints II
38:55
35
Technology Mapping
30:36
36
Timing-driven Optimization
49:43
37
Technology Library and Constraints
18:05
38
Power Analysis
47:16
39
Power Optimization
37:47
40
Basic Concepts of DFT
51:53
41
Scan Design Flow
42:18
42
Power Analysis using OpenSTA
17:49
43
Automatic Test Pattern Generation (ATPG)
47:06
44
Built-in Self Test (BIST)
45:27
45
Basic Concepts for Physical Design - I
1:01:41
46
Basic Concepts for Physical Design - II
36:49
47
Installation of OpenRoad
6:05
48
Chip Planning - I
1:00:43
49
Chip Planning - II
51:33
50
Placement
43:19
51
Chip Planning and Placement
17:24
52
Clock Tree Synthesis (CTS)
48:28
53
Routing
1:04:44
54
Post-layout Verification and Signoff
44:31
55
Clock Tree Synthesis (CTS) and Routing
13:32
56
Live
1:30:21
